Implementation of an SVD Based MIMO OFDM channel estimator
This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm 2 design. This corresponds to ~30 M estimates per second, which i