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A time-interleaved ADC analog front-end is presented with a sampling rate of 64GS/s. It has a hierarchical architecture of 2-4-4 giving 32 separate channels. Each channel is constructed by an input buffer, 1st rank (T/H), sub-buffer, and 2nd rank T/H. The complimentary clocking generation consist of a 32GHz differential signal divided down using a CML divide-by-4 and DFF divide-by-4 architecture.
