Design of a 13-Bit SAR ADC with kT/C noise cancellation technique
One of the main limitations of a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is the large input capacitance needed to achieve the desired performance. This large input capacitance increases the total area of the ADC and it imposes the use of a powerful buffer to drive it. Since the input capacitance is inversely proportional to the kT/C noise, reducing it, generates m