Source Design of Vertical III-V Nanowire Tunnel Field-Effect Transistors
We systematically fabricate devices and analyse data for vertical InAs/(In)GaAsSb nanowire Tunnel Field-Effect Transistors, to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb source segments improved the transistor metrics (subthreshold swing and the ON-current performance), due to
